The invention relates to a method of manufacturing an integrated circuit on a substrate, which method comprises steps for forming a high electron mobility transistor (HEMT), these steps including the realization of a succession of layers provided on the substrate, among which are at least a layer of a material having a narrow bandgap which is weakly doped for forming the channel of the transistor and a donor layer of a material having a wide bandgap which is strongly doped for providing electrons, these steps also including the realization of an insulation zone completely surrounding the transistor relative to the other elements of the integrated circuit and the realization of gate, source and drain electrodes.
The invention has its application in the manufacture of digital or analog integrated circuits.
A process as described above is known from the publication by April S. Brown et al. of the Hughes Research Laboratories, entitled "Low-Temperature Buffer AlInAs/GaInAs on InP HEMT Technology for Ultra-High-Speed Integrated Circuits", published in "1989 IEEE GaAs Ic Symposium", pp. 143-146.
The cited document describes a process for realizing an integrated circuit including the formation of a high electron mobility transistor. This process comprises the realization on a substrate of semi-insulating InP of a succession of layers, in that order: a buffer layer of AlInAs n.sup.-, a channel layer of GaInAs n.sup.-, a separating layer of AlInAs n.sup.-, a donor layer of AlInAs n.sup.+, (strongly doped), a layer suitable for receiving a Schottky contact and made of AlInAs n.sup.-, and an encapsulating layer of GaInAs.
After the layers have been formed, two contacts of the ohmic type are realized for forming the source and drain of the transistor at the surface of the encapsulating layer. Then a groove is etched between the source and the drain down to the said Schottky layer and a Schottky-type contact is realized by means of a metallization in this groove so as to form the gate of the transistor by self-alignment.
The cited document teaches that two techniques are possible for insulating the transistor from other elements of the integrated circuit.
The first method indicated is insulation by the formation of a mesa, i.e. by the realization of an etched portion completely surrounding the transistor region, which etched portion delimits the transistor whose active region accordingly is present in relief relative to the substrate. In these conditions it is necessary for the metallization of the Schottky gate to follow the flank of the mesa for connecting the gate to a gate contact pad disposed in the vicinity of the transistor in the region of the substrate which appears after etching of the mesa, as is shown in FIG. 3 of the cited document.
This arrangement of the connection between the gate metallization and its contact pad leads to a serious problem, for the connection metallization is in contact with all the layers which reach up to the flank of the mesa, particularly the strongly doped AlInAs n.sup.+ layer, so that during operation the transistor suffers from a strong leakage current, as is shown in FIG. 2 of the cited document.
According to this document, this leakage current is avoided in that the transistor is insulated not by the formation of a mesa but by a second method comprising an implantation of ions around the active zone, which results in the device remaining planar.
The second solution indicated, however, is not favored by those skilled in the art of manufacturing integrated circuits. In fact, ion implantation for the realization of insulation requires burdensome technical means consisting of an ion implantation device; moreover, it requires a heat treatment which tends to deteriorate the characteristics of the layers or of other devices of the integrated circuit already realized; furthermore, ion implantation is not fully reproducible; in addition, its effectivity is less than that of a mesa. All these facts mean that firstly the useful manufacturing output of integrated circuits with the inclusion of the steps for insulating by ion implantation may be severely limited instead of reaching figures as figures as close as possible to 100%, as is the target for the manufacturer of integrated circuits, and secondly that the cost of the integrated circuit is high.
Those skilled in the art thus find themselves confronted with the problem of how to avoid the ion implantation steps, and consequently of how to form the insulating mesa. This then involves the double problem
of realizing a transistor without leakage currents, and PA1 of realizing this transistor without increasing the number of steps in the manufacturing process. PA1 providing a mask at the surface of the superimposed layers, which mask covers and defines the active zone of the transistor; PA1 etching the superimposed layer structure down to the substrate with underetching under the mask so as to insulate the active zone by means of a mesa; PA1 realizing a dielectric layer by uniform deposition; PA1 etching the dielectric layer directionally while maintaining the portions of this layer which are protected by the mask as a result of the under-etching and are disposed on the flanks of the mesa around the active zone of the transistor; and PA1 eliminating the mask. PA1 insulation of the gate connection from the strongly doped layer as well as from the other layers thanks to the dielectric layer, resulting in the reduction of leakage currents to the same extent as in the known process; PA1 improvement of the other performance characteristics of the transistor compared with those of the known transistor owing to a better insulation of this transistor from the other components realized on the substrate; PA1 an increase in the useful manufacturing output owing to a smaller dispersion of characteristics of the components caused by a better insulation of each transistor and by the simplicity of the manufacturing process; and PA1 reduction on the one hand of the cost of the equipment necessary for realizing the integrated circuits, since it is not necessary to provide an ion implantation device, and on the other hand of the manufacturing cost itself because of the high useful manufacturing output and the simplicity of the process.
In fact, each increase in the number of steps can result in an accumulation of disadvantages: i.e. the manufacturing cost is increased while at the same time the useful manufacturing output is reduced, which in its turn further increases the ultimate manufacturing cost.
Given the present competitive situation among manufacturers of integrated circuits, the least increase in cost can result in a total loss of the market. It is thus of the greatest possible importance to minimize these costs. That which may seem at first sight to be only a detail in the manufacturing process, or, still at first sight, an equivalent step, may turn out to be a factor of economic disaster for the manufacturer of integrated circuits, or alternatively a means of maintaining his position on the market, as the case may be.